Content originally posted in LPCWare by ehughes on Sun Aug 23 13:39:06 MST 2015
I wanted to post an update to this issue. For the longest time I have been using the "hand tuned" PLL value but very uncomfortable with it. There were some units that came from assembly with wierd issues that were tracked down to the PLL not initializing correctly. Below is the code that works.
Notes:
1.) The PLL must be disabled before setting the 1st values.
2.) After setting it up, it was necessary, to enable disable and re-enable.
3.) After #2, I woudl have a look that checks the lock bit and will chip disabling and reenabling the lock bit. I honestly don't think the lock bit works correctly as the PLL still outputs a correct value (verified with a frequency counter) when the lock bit isn't set
4.) If the PLL setup is done on the board library, I noticed it would take 3 to 5 retires to get a lock. If the routine is done a few milliseconds after reset, it takes fewer resets to get a lock (i.e. but it after main).
void InitAudioPLL()
{
uint8_t LockRetries = 0;
CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup;
Chip_Clock_DisablePLL(CGU_AUDIO_PLL);
audioPLLSetup.ctrl = (0x06<<24) //Crystal OSC as input to Audio PLL
| (1<<11) //Enable Autoblock
| (1<<4) //PLL Clock Enable
| (1<<12); //Enable Fractional Divider
audioPLLSetup.ndiv = ((3)<<0) //Pdec
| ((1)<<12); //Ndec
audioPLLSetup.fract = 0x1a1cac;
//audioPLLSetup.fract = 1342168; //hand tuned weird value
Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
Delay_mS(50);
Chip_Clock_EnablePLL(CGU_AUDIO_PLL);
Delay_mS(50);
while( LockRetries<5
&& ((Chip_Clock_GetPLLStatus(CGU_AUDIO_PLL) & 0x01) == 0)
)
{
Chip_Clock_DisablePLL(CGU_AUDIO_PLL);
Delay_mS(50);
Chip_Clock_EnablePLL(CGU_AUDIO_PLL);
Delay_mS(50);
if(Chip_Clock_GetPLLStatus(CGU_AUDIO_PLL) &0x01)
{
break;
}
else
{
LockRetries++;
}
}
if(LockRetries >= 5)
{
//Debug Here
}
}