Incorrect Audio PLL Behavior - **FIXED**

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by ehughes on Tue Apr 29 04:50:34 MST 2014
I am seeing goofy behavior from the Audio PLL in the LPC4357.

The frac value in the user manual & generated by the pll_dialog tool produce incorrect values.  I first started with NP_DIV & fractional values from page 189,, Rev 1.8 of UM10503.

I am using the Keil MCB4357 Board Library with a 12MHz input clock.  I first tried to get a 12.288Mhz output clock.

Here is the code that sets up the Audio PLL:

    audioPLLSetup.ctrl =   (1<<11) //Enable Autoblock
            | (1<<4)  //PLL Clock Enable
| (1<<12); //Enable Fractional Divider

audioPLLSetup.ndiv = ((3)<<0)   //Pdec
  | ((1)<<12);  //Ndec

audioPLLSetup.frac = 0x1a1cac;

Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_AUDIO_PLL, &audioPLLSetup);


also, in the CLK_BASE_STATES structure, I route the audio PLL output to CGUOUT0


This configuration returns a frequency of 15.63Mhz!

So,  I double checked the CGU settings in the debugger and also checked the values again what the PLL_Dialog tool produces.

I tried a could other values for audioPLLSetup.frac and could see the frequency move.   The is a linear relationship between the fracvalue and what I get on the CGUOUT0 pin.

frac value    Measured Frequency
0x1a1cac<<1   31.25MHz
0x1a1cac      15.72MHz
0x1a1cac>>1   7.813MHz

3 other observations:

1.  The Lock bit in the STAT register never goes active (it appears that the signal is stable and is not hunting around).

2.  even though I set the PLLFRACT_REQ in the CTRL register, it appears to always read back as zero in the debugger.

3.)   If I use normal MDEC mode,  the output frequency is at around 60Mhz!   This uses the setting from the PLL dialog tool.

Any pointers?    I can manually find my setpoint by trial and error but I would really like to understand what is happening.