Content originally posted in LPCWare by kiyoong on Mon Sep 14 18:13:03 MST 2015
Dear NXP Support Team,
Thank you for sharing SGPIO example.
Q1) 2 slice buffer would be necessary for 1 channel of I2S ?
In this example, 4SGPIO pins was used for a four channel I2S TX. However, each I2S channel needed 2 slice buffer of SGPIO. refer to the source code below.
--------
LPC_SGPIO->SGPIO_MUX_CFG[1] =
LPC_SGPIO->SGPIO_MUX_CFG[12] = CONCAT_ENABLE | SLICE_2;
LPC_SGPIO->POS[1] =
LPC_SGPIO->POS[12] = ((0x020*2 - 1) << 8) | (0x020*2 - 1);
LPC_SGPIO->OUT_MUX_CFG[9] = 0;// output the data bit on SGPIO9
-------------
Does it mean that 2 slice buffer would be necessary for 1 channel of I2S ?
If then, we could make 7 output channels with 16 slice buffers. Am I right ?
Q2) Could it be possible to implement Tx and Rx, and Use it at the same time ?
Actually, we are supposed to build TX and RX channels.
In this case, I think ~~
1 frame sync,
1 clock,
3 TX channels (with 2 slice buffers each )
--- totally 8 pins and slice buffers for TX. Of course RX part will equal to TX.
therefore, 3 TX and 3 RX are the maximum count of SGPIO.
Is My understanding correct ? Is it possible ?
Sorry for bothering with too many questions.