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- LPC4357-EVB Development Kit debug in SDRAM
LPC4357-EVB Development Kit debug in SDRAM
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LPC4357-EVB Development Kit debug in SDRAM
lpcware
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Hello.
<p style="background-image: initial; background-attachment: initial; background-origin: initial; background-clip: initial; background-color: transparent; border-style: initial; border-color: initial; border-collapse: collapse; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; font-size: 1em; list-style-type: none; list-style-position: initial; list-style-image: initial; outline-width: 0px; outline-style: initial; outline-color: initial; background-position: initial initial; background-repeat: initial initial; border-width: 0px; padding: 0px; margin: 0px;">Somebody has a *.mac-file for debug in SDRAM with Jlink in IAR for this board or some else board with LPC43xx.
<p style="background-image: initial; background-attachment: initial; background-origin: initial; background-clip: initial; background-color: transparent; border-style: initial; border-color: initial; border-collapse: collapse; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; font-size: 1em; list-style-type: none; list-style-position: initial; list-style-image: initial; outline-width: 0px; outline-style: initial; outline-color: initial; background-position: initial initial; background-repeat: initial initial; border-width: 0px; padding: 0px; margin: 0px;">I will be very grateful.
<p style="background-image: initial; background-attachment: initial; background-origin: initial; background-clip: initial; background-color: transparent; border-style: initial; border-color: initial; border-collapse: collapse; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; font-size: 1em; list-style-type: none; list-style-position: initial; list-style-image: initial; outline-width: 0px; outline-style: initial; outline-color: initial; background-position: initial initial; background-repeat: initial initial; border-width: 0px; padding: 0px; margin: 0px;">
<p style="background-image: initial; background-attachment: initial; background-origin: initial; background-clip: initial; background-color: transparent; border-style: initial; border-color: initial; border-collapse: collapse; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; font-size: 1em; list-style-type: none; list-style-position: initial; list-style-image: initial; outline-width: 0px; outline-style: initial; outline-color: initial; background-position: initial initial; background-repeat: initial initial; border-width: 0px; padding: 0px; margin: 0px;">
lpcware
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Here is my *.mac file.
I tried to debug, Iar sayd:
Tue Apr 16, 2013 16:55:48: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\LPC43xx_extRAM.mac
Tue Apr 16, 2013 16:55:48: Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac
Tue Apr 16, 2013 16:55:48: Logging to file: D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\cspycomm.log
Tue Apr 16, 2013 16:55:48: JLINK command: ProjectFile = D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\settings\LCD_ExtSDRAM_LPC4350_IntSRAM.jlink, return = 0
Tue Apr 16, 2013 16:55:48: JLINK command: scriptfile = C:\Program Files\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\LPC4350_DebugCortexM4.JLinkScript, return = 0
Tue Apr 16, 2013 16:55:48: Device "LPC4357_M4" selected (0 KB flash, 0 KB RAM).
Tue Apr 16, 2013 16:55:48: DLL version: V4.56b, compiled Nov 7 2012 18:44:28
Tue Apr 16, 2013 16:55:48: Firmware: J-Link V9 compiled Jan 11 2013 12:33:03
Tue Apr 16, 2013 16:55:48: JTAG speed is using adaptive clocking (RTCK signal)
Tue Apr 16, 2013 16:55:48: NXP LPC4350 (Cortex-M4+M0 core) J-Link script
Tue Apr 16, 2013 16:55:48: TotalIRLen = 8, IRPrint = 0x0011
Tue Apr 16, 2013 16:55:48: J-Link script: Cortex-M0 already enabled.
Tue Apr 16, 2013 16:55:48: TotalIRLen = 8, IRPrint = 0x0011
Tue Apr 16, 2013 16:55:48: Found Cortex-M4 r0p1, Little endian.
Tue Apr 16, 2013 16:55:48: TPIU fitted.
Tue Apr 16, 2013 16:55:48: ETM fitted.
Tue Apr 16, 2013 16:55:48: FPUnit: 6 code (BP) slots and 2 literal slots
Tue Apr 16, 2013 16:55:48: Found Cortex-M4 r0p1, Little endian.
Tue Apr 16, 2013 16:55:48: TPIU fitted.
Tue Apr 16, 2013 16:55:48: ETM fitted.
Tue Apr 16, 2013 16:55:48: FPUnit: 6 code (BP) slots and 2 literal slots
Tue Apr 16, 2013 16:55:48: Hardware reset with strategy 0 was performed
Tue Apr 16, 2013 16:55:48: Initial reset was performed
Tue Apr 16, 2013 16:55:48: Found 2 JTAG devices, Total IRLen = 8:
Tue Apr 16, 2013 16:55:48: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Tue Apr 16, 2013 16:55:48: #1 Id: 0x0BA01477, IRLen: 4, IRPrint: 0x1 CoreSight SW-DP
Tue Apr 16, 2013 16:55:48: execUserPreload
Tue Apr 16, 2013 16:55:49: not fail
Tue Apr 16, 2013 16:55:49: execUserPreload Finish
Tue Apr 16, 2013 16:55:49: 7820 bytes downloaded and verified (30.55 Kbytes/sec)
Tue Apr 16, 2013 16:55:49: Warning:
Verify error at address 0x28000000, target byte: 0x00, byte in file: 0x08
.....
Tue Apr 16, 2013 16:55:49: Warning:
Verify error at address 0x280000CC, target byte: 0xFF, byte in file: 0x35
Tue Apr 16, 2013 16:55:49: Warning: Too many verify errors, only the first 200 are displayed
Tue Apr 16, 2013 16:55:50: Warning: There were warnings during download, see Log Window
Tue Apr 16, 2013 16:55:50: Loaded debugee: D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\LPC4350_IntSRAM\Exe\LCD_ExtSDRAM.out
Tue Apr 16, 2013 16:55:52: Fatal error: Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Command : 10) @ Off 0x5. Wrong AHB ID (15:3). Expected 0x04770001 (Mask 0x0FFFFF0F), Found
0x00000000 Session aborted!
Tue Apr 16, 2013 16:55:52: Target reset
Tue Apr 16, 2013 16:55:52: Failed to load debugee: D:\Documents\ÌÊ\LPC43xx\LPC4300-demos\Examples\LCD_ExtSDRAM\EWARM\LPC4350_IntSRAM\Exe\LCD_ExtSDRAM.out
Times and delays for initialization are taken from an example that works. What am I doing wrong?
