Content originally posted in LPCWare by pdv on Mon Apr 06 13:06:05 MST 2015
Hi everyone,
I've tried to implement the "I2S MCLK slave mode" example described in the UM (version 1.9) under §20.8.1, see page 499.
I've come to the conclusion that this cannot work. Under item 2. the UM says:
"2. MCK master mode: MCK is supplied at pin 12 to slice D, where this clock is divided by the oversampling rate (=4). The output of slice D is used as shift clock for the other slices."
In the end this seems to be wrong in all respects:
- It's already strange to call this "master mode" since it's the 2nd possiblity of the "I2S slave mode" (thus slave to MCLK).
- pin 12 cannot serve as a clock input (only pins 8-11 can); This is corrected in the label of Table 324, where pin 9 is mentioned.
- an externally supplied clock cannot be divided using the PRESET setting as in Table 324 (see Fig 46), so the only way to divide it by 4 is by loading the REG/REG_SS with the proper values (e.g. 0xCCCCCCCC) and using the data output of the slice D as a clock; which is indeed suggested by the last sentence;
Slices D,H,O,P can serve as a clock source for other slices and the above example suggests that it is the data output of these slices which serves as the clock; But fig 45 suggests otherwise: when slice D is used as a clock source it means that the shift-clock of slice D is used as the clock for another source; (at least that's my understanding for the moment).
If this is correct then there is no way to divide an externally supplied clock in the way described in the example.
I would be grateful if someone knowledgable could confirm or correct this.
Regards,
