lpcware

Undocumented SPIFI Interrupt Handler

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by avenuti on Wed Jan 06 14:28:21 MST 2016
UM10430 LPC18xx ARM Cortex-M3 microcontroller
Rev 2.8 - 10 December 2015

This user manual is missing information on the SPIFI Interrupt Handler.

In table 72, Chapter 8 (NVIC), Interrupt ID 30 is listed as "Reserved", but enabling this bit in NVIC->ISER[0] enables the SPIFI interrupt.
(The corresponding table in the manual for LPC43xx lists this as the SPIFI interrupt)

Furthermore, cmsis_18xx.h in lpc_chip_18xx in LPC OPEN lists this RESERVED4_IRQn, but calling NVIC_EnableIRQ(RESERVED4_IRQn); also correctly enables the SPIFI interrupt.

cr_startup_lpc18xx.c does declare SPIFI_IRQHandler(), which leads me to believe this interrupt is meant to be supported.


Is this simply a mistake in the manual, or is this feature unsupported?
If it is unsupported, why does the manual list INTEN in table 336 and and INTRQ in table 343, both in Chapter 21 (SPIFI)?

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