lpcware

about LPC17xx emac Overrun error

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by ml1234 on Sat Feb 23 02:10:32 MST 2013
1.
LPC17xx User manual Rev.2 Page 190, about this bit:

The data flow on the receiver data interface stalls, corrupting the packet.
In this case the overrun bit in the status word is set and the RxError bit in the IntStatus register is set.
This error is nonfatal.

what reason can have this bit set?

2.
The flow of reception statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface.
This error will corrupt the hardware state and requires the hardware to be soft reset.
The error is detected and sets the Overrun bit in the IntStatus register.

how to reset the hardware?

thx!
2013-2-23

Outcomes