Content originally posted in LPCWare by wella-tabor on Sun Aug 23 09:00:38 MST 2015
Quote: wmues
I do not know where you have read about MLCK.
I have read it here: UM10470, Rev. 3.1, page 463.
Table 348. MCI Clock Control register (CLOCK - address 0x400C 0004) bit description
Bit Symbol
7:0 CLKDIV
Value Description
Reset
Value
Bus clock period:
0
SD_CLK frequency = MCLK / [2 ́(ClkDiv+1)].
..............
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
BR
Martin