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LPC1778 SWD SWCLK Pull Up or Pull Down

Question asked by lpcware Employee on Jun 15, 2016
Latest reply on Oct 31, 2016 by Olivier Martin
Content originally posted in LPCWare by MikeSimmonds on Thu Nov 06 23:38:33 MST 2014
Hi we are about to make revised PCB for our custom 1778 board to fix errors/problems.

However, before the lasted PCB is finalised, I have noticed a contradiction in  the requirements
for the SWD SWCLK signal.

In this FAQ "Design Considerations for Debug" at http://www.lpcware.com/content/faq/lpcxpresso/debug-design
it shows a pull DOWN on the clock line.

JTAG Mode SWD Mode Signal Notes
TCK SWCLK Clock into the core Use 10K-100K Ohm pull-down resistor to GND


In the latest UM10470 for LPC178x/7x Fig 176 "Cortex Debug Connector" it shows a pull UP
[Also in UM10503]

The schematic for the e.g the MCB1700 board uses a pull down.

Our board in revisions A and B use a pull down and debug certainly works with the original LPC-Link
and with LPC-Link2 (Redlink)

So what is the OFFICIAL requirements.
Is it the user manual(s) or the FAQ in error?

And does it really matter after all is said and done?

Regards Mike

NXP: If you could answer promptly, as we need to get these PCB's made soonest.





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