Content originally posted in LPCWare by noahk on Mon May 12 11:12:31 MST 2014
Hi Dennis,
I am confused by the last polling line. It looks like you are polling for TxRdy, and not Idle:
// This one is never false?
while( (LPC_SPI0 -> STAT & (1<<1)) == 0); // Wait for all data to be transmitted
The Idle bit is set once the transfer is complete (EOT done). Does that explain the behavior you are seeing? If you truly want to know that the tx shifting is done, you might use receive data to be sure that you got data back. That will work for modes where rx follows tx, like mode 1 and mode 3 (CPHA == 1). But for modes where tx follows rx, the receive data will come in before the final shift is done. Due to stall logic, you will never get the final transmit edge until you provide the next buffer (if there was no EOT). But the lines will be stable, and perhaps you can make your changes without adverse effects in that situation.
Noah