Content originally posted in LPCWare by riscy00 on Wed Aug 12 11:52:29 MST 2015
Hi
I'm trying to figure out why the I2CM polling demo code set the CLKDIV = 40 which equate to 1.8MHz (SYSCLK/40 = 72MHz/40 = 1.8MHz)
Chip_I2C_SetClockDiv(LPC_I2C0, I2C_CLK_DIVIDER);
where
/* I2C clock is set to 1.8MHz */
#define I2C_CLK_DIVIDER (40)
I read user guide and demo code twice and could not see why or reason to reduce I2C clock to 1.8MHz. Furthermore, the demo does not seem to follow user guide which state on section 26.4.1
Divide the system clock (I2C_PCLK) by a factor of 2. See Table 382 “I2C Clock Divider register (CLKDIV, address 0x4005 0014) bit description”.
Can you please clarify how to setup demo code for I2C_CLK_DIVIDER for 100KHz, 400KHz and 1MHz.
Thanks
PS: I2CM_polling demo code come from lpcopen_2_08c_lpcxpresso_nxp_lpcxpresso_1549.zip (Most recent)
