Content originally posted in LPCWare by NXP_Paul on Wed May 08 13:39:00 MST 2013Hello Sariga
First, you need to determine the clock to the I2C peripheral which is PCLKI2C. Looking at Figure 3 in the UM10524 User's Manual, you will see that the clock to the I2C peripheral is the main clock divided by the system clock divider. You didn't specify what your main clock was set to, but let's assume that you are using the PLL to bring the clock speed up to 72MHz. Most of the time, the system clock divider (SYSAHBCLKDIV) is set to '1', so then the I2C peripheral block will also be 72 MHz. Don't forget to enable the clock to the I2C peripheral by setting bit 5 in SYSAHBCLKCTRL to '1'.
If you want to get 100kHz from the I2C clock, the equation becomes:
SCLH + SCLL = (PCLKI2C)/(I2C bit frequency) = (72MHz)/(100kHz) = 720
So, the total of the SCLH and SCLL registers should be 720. The easiest thing to do is split it evenly between the two, and therefore load the value 360 into each of the SCLH and SCLL registers.
The I2C specification states that the minimum clock low time for a 100kHz bus should be 4.7us while the minimum clock high time is 4.0 us. The low and high times for this configuration will be 360/72MHz=5.0 us, so we can meet both the I2C clock low and high requirements.
Hopefully that makes things easier to understand.
