Hello,
just 2 quick (dumb) questions :)
- 14.7.5 SSP Clock Prescale Register -- 'In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock...' -- does this mean that when my LPC is running on 72 MHz, then maximum clock (SCK) in SPI slave mode can be 6 MHz? (~ 6 Mbit, 0.75 MB/s)
- does the SPI CS line have to toggle (go H and L) for every received byte in SPI slave mode? (found somewhere here, on forum).
Jookie
Rolf,
thank you for reply, I somehow missed that CPHA=1 part in user manual. That CPHA=1 would help me, but that 6 MBit/s thing will force me to move to a different MCU, because I need to implement SPI slave for 16 MHz SCK. Too bad that I've hit this problem at the end of writing code - I've left the SPI part as last one, because I thought there can't be any problem, and I didn't check the manual soon enough :) That /12 rule would push my 16 MHz SCK to 192 MHz PCLK which is not possible with LPC1343, and it seems that any other LPC MCU doesn't go so high either...
Regards,
Jookie
Hi Jookie,
6 MBit/s (=72 MHz / 12) is indeed the fastest clock speed for the SSP in slave mode.
The SSEL line must toggle between frames only in SPI modes 0 and 2, i.e. the modes where CPHA=0. This is enforced by the SSP in slave mode, and it will ignore the second and any further frame if you do not toggle SSEL in between.
SPI modes 1 and 3 (where CPHA = 1) can have SSEL continuosly low for multiple frames.
Regards,
Rolf