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MPC5125 Power on Reset

Question asked by Luigi Benciolini on Apr 29, 2016
Latest reply on May 4, 2016 by Luigi Benciolini

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In reference to a CPU board equipped with NXP MPC5125YVN400 we found a malfunction at startup reset (PORESET)

The problem involves the boards equipped with processor with marking code QAT1535C.

Currently no problem are found on boards equipped with processor with marking code DAR1532AF.

Extending the reset time from 180mS up to 220mS (or more) the problem disappear; --> consider that the datasheet don't impose any constraint regarding the PORESET timing (Obviously is requred that PORESET can be released after all the supplies reach the specified operating conditions).

Enclosed you find some oscilloscope screenshot

Thank You nn advance

Luigi

Pavel Chubakov

May 3, 2016 9:56 PM

Correct Answer

Usually similar behavior detected if the following happens on the board:

power supply is not stable,

the MPC5125 PLL is not locked

the MPC5125 reset configuration incorrectly read.

Look at the Figure 5 of the MPC5125 Datasheet.

Is there the same behavior of the HRESET and SRESET on your board during power up?

Look at the Figures 51 and 52 of the MPC5125 Datasheet.

Do you use similar connection on your board?

If the second short PORESET is solution of your problem, power supply is not stable or the MPC5125 PLL is not locked during 182ms.

Have a great day,
Pavel Chubakov

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Pavel Chubakov

May 3, 2016 9:56 PM

Usually similar behavior detected if the following happens on the board:

power supply is not stable,

the MPC5125 PLL is not locked

the MPC5125 reset configuration incorrectly read.

Look at the Figure 5 of the MPC5125 Datasheet.

Is there the same behavior of the HRESET and SRESET on your board during power up?

Look at the Figures 51 and 52 of the MPC5125 Datasheet.

Do you use similar connection on your board?

If the second short PORESET is solution of your problem, power supply is not stable or the MPC5125 PLL is not locked during 182ms.

Have a great day,
Pavel Chubakov

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Luigi Benciolini @ Pavel Chubakov on Jun 24, 2016 12:47 AM

Pavel,

Thank you for quick and useful answer.

Regarding your questions, the answer are:

1) The beahvior of HRESET and SRESET is congruent to that one showed in figure 5 (and Table 19) anyhow (both when the board starts correctly or not)

2) The connection of our schema is the same to that reported in figure 52

Other informations:

3) In effect +1V8 is not monotonic during rise time.

We tried to supply externally in order to guarantee monotoniticy but the problem is not solved.

However, there is still a violation in the slew rate of the power supplies (faster than required in datasheet §.5.1=max 12V/ms).

I'll try as soon as possible also to reduce the power supply slew rate and repeat the test.

The Sequencing is correct (VDD core last)

4)The current workaround that we implemented is to enable the internal watchdog before than the processor address to the DDR2. With this workaraound the "problematic" board starts correctly for more than 400 times (test executed with automatic equipment).

Luigi

As anticipated in the previous point 3), we tried to supply the CPU with a new DCDC stage with soft start in order to guarantee the slew rate less than 12V/ms.

The board now works fine. So I confirm that the problem was the violation of the power supply slew rate.

Luigi

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Pavel Chubakov May 3, 2016 9:56 PM
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Correct Answer
Usually similar behavior detected if the following happens on the board:
power supply is not stable,
the MPC5125 PLL is not locked
the MPC5125 reset configuration incorrectly read.
Look at the Figure 5 of the MPC5125 Datasheet.
Is there the same behavior of the HRESET and SRESET on your board during power up?
Look at the Figures 51 and 52 of the MPC5125 Datasheet.
Do you use similar connection on your board?

If the second short PORESET is solution of your problem, power supply is not stable or the MPC5125 PLL is not locked during 182ms.

Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
1 person found this helpful
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- Luigi Benciolini @ Pavel Chubakov on Jun 24, 2016 12:47 AM
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  Correct Answer
  Pavel,
  Thank you for quick and useful answer.
  
  Regarding your questions, the answer are:
  1) The beahvior of HRESET and SRESET is congruent to that one showed in figure 5 (and Table 19) anyhow (both when the board starts correctly or not)
  2) The connection of our schema is the same to that reported in figure 52
  
  Other informations:
  3) In effect +1V8 is not monotonic during rise time.
  We tried to supply externally in order to guarantee monotoniticy but the problem is not solved.
  However, there is still a violation in the slew rate of the power supplies (faster than required in datasheet §.5.1=max 12V/ms).
  I'll try as soon as possible also to reduce the power supply slew rate and repeat the test.
  The Sequencing is correct (VDD core last)
  4)The current workaround that we implemented is to enable the internal watchdog before than the processor address to the DDR2. With this workaraound the "problematic" board starts correctly for more than 400 times (test executed with automatic equipment).
  
  Luigi
  
  As anticipated in the previous point 3), we tried to supply the CPU with a new DCDC stage with soft start in order to guarantee the slew rate less than 12V/ms.
  The board now works fine. So I confirm that the problem was the violation of the power supply slew rate.
  
  Luigi
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MPC5125 Power on Reset

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