I have a couple questions.
- When looking at the MPC8347EA Power QUICC Hardware Specifications (Revision 12), I notice that when the local bus is in GPCM & DLL Bypass mode, all of the timing parameters are in reference to the falling edge of LCLK. However, in the MPC8349EA Power QUICC Family Reference Manual, diagrams seem to to show local bus transactions as if they were in relation to the rising edge of the clock. For example, look at Figure 10-29 on page 476 of the reference manual.
- Are the diagrams in the reference manual assuming that the DLL is enabled? So, if the DLL was bypassed, figure 10-29 would have transitions on the falling edge of the clock instead of the rising edge (LAD changes from address to data)?
- The Hardware Specifications Figure 22 for Local Bus signals in DLL Bypass mode only shows tLBKHOZ (Local bus clock to output high impedance for LAD/LDP). However, if you look at diagrams in the reference manual, LAD is transitioning directly from Address to Data. Is there a clock cycle of Hi-Z inbetween address and data output, or does the LAD bus transition directly from Address to data? If so, how do I reconcile this with tLBKHOZ? Could I instead use tLBKLOV on the next cycle to determine when the Address transitions to data?
- Lastly, I could not find any location in the reference manual that defines when LWE is asserted (it says when it is negated). My best guess is going from Figure 10-29, it seems like LWE is asserted for...
LWE_duration = SCY + TRLX + 1 -(1/4*CSNT);