i.MX6Q: apb_slave and qv_value for MPCore-2 and 3

[norishinozaki]

Hello Champs,

In the RM, "Table 45-5. QoS and tidemark parameters"

I found entries for MPCore-0 and 1.

What is apb_slave and qv_value for MPCore-2 and 3?

Regards,

Nori Shinozaki

[igorpadykov]

Hi Nori

MPCore-0 does not mean arm core 0. Meaning is AXI (number 0) of

MPCore platform. That is internally 4xcores are connected to SCU,

SCU is connected to L2 cache, L2 has two AXI buses named as

"MPCore-0,1" connected to NIC GPV_0. Short RM description is below

Best regards

igor

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[norishinozaki]

Thanks Igor,

So when we change the priority of Cortex A9 cores, we change qv_value for both MPCore-0 and 1 at a time.

Correct?

Best regards,

Nori Shinozaki

[igorpadykov]

Hi Nori,

this does not relate to A9 cores, it relates to L2 AXI buses (0 and 1),

for its usage one can refer to documetation of L2 cache controller

like ARM document DDI0246A PL310 and other L2 documentation.

Best regards

igor

[norishinozaki]

Igor,

Thanks, I found this diagram.

BR,

NS