There seems to be some discrepancy in the Freescale documentation regarding the frequency for the P2020 SYSCLK frequency.
In AN4261 rev4, Table 10 states the SYSCLK pin must always be connected to an input clock of 66 - 100 MHz. However, in the P2020 datasheet rev2, the minimum SYSCLK frequency is specified at 64 MHz. Additionally, the Integrated Ref Manual rev2 12/2012 in section 220.127.116.11 states that we can use a frequency below 66 MHz as long as we take care of the cfg_sys_speed register on power up.
So is it okay to go below 66 MHz?