Hello, we have an external 16-bit Async memory connected to the FlexBus interface on the MK20FN1M0VMD12. For the speed grade memory we are using, we can either operate the Flexbus at 30 MHz with 0 wait states, or 40 MHz with 1 wait state. On the surface, it would appear overall throughput would be slightly better at 40 MHz+1WS (5 clock cycles total for a transaction time of 125 ns) vs 30 MHz+0WS (4 clock cycles for a total of 133.3 ns). However, in throughput testing performed by our software team, they noticed ~15% better throughput when running at 30 MHz+0WS. Based off of the calculations above, this seems counter intuitive. Is it possible that the addition of a wait state adds additional delays beyond the 5th clock for each memory access? Any insight would be greatly appreciated, Thanks in advance.