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MIPI CSI2: Frame Capture Error: Custom i.MX6Q Platform (Xilinx Artix7 FPGA with i.MX6Q)

Question asked by SHAJIN AS on Jan 13, 2016



I am working on a custom platform which is based on i.MX6Q + Xilinx Artix7.It is ported with Android Kitkat 4.4.3.

I'm having issues with frame capture on MIPI CSI2.


Custom Platform Details :-


In the custom platform the Artix7 FPGA acts as CSI2 2 lane transmitter, which constantly streams out YUV422 data @720p 30fps, 200MHz (DDR - Discontinuous Clock) to i.MX6Q. The below figure shows the mipi csi connectivity between i.MX6Q and Xilinx Artix7.



We took the ov5640_mipi driver and removed the i2c sections as the FPGA pumps streams data on enabling a GPIO line. We tried to capture the frame using v4l2 frame capture utilities the timeout error occurs. "ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0".


Questions :-


1) As per the "Debug steps for customer MIPI sensor.docx" document we dumped the MIPI CSI Registers. We noticed difference in register values as compared to i.MX6Q SABRESD platform with ov5640. By continuously monitoring the MIPI_CSI_PHY_STATE register, we noticed register values vary between 0x300(More Prominent), 0x330,0x630 and 0x230.  Attached mipi_dump.txt which contains the MIPI_CSI_PHY_STATE register and MIPI_CSI_ERR1 register. Since the register value 0x300 is more prominent, Does this confirms that the i.MX6Q MIPI controller receiving valid MIPI clock and Data ?


2) Also we are noticing the MIPI_CSI_ERR1 register value was set to 0x01001000 (Please refer the mipi_dump.txt). On looking at the description of MIPI_CSI_ERR1 bits, CRC error was set on Virtual Channel 0. Is this error represents captured data doesn't match with the CRC cheksum field in MIPI CSI Packet ?

Is there any way to disable the MIPI CSI CRC error check ? We tried masking the crc error bits in MIPI_CSI_MASK1 register. But, even then we got the same CRC error. Is there anything i missed out ?


3) Can we operate MIPI Reciever (i.MX6Q) in HS Mode only?


4) From the Linux BSP we found the MIPI dphy clock is configured to 198MHz. I was wondering if this is sufficient to capture the frame from the MIPI CSI Transmitter which was operating at DDR Mode in 200MHz ?




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