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iMX6 memory copy

Question asked by Vadim Ignatov on Dec 16, 2015
Latest reply on Dec 16, 2015 by Yuri Muhin

Hello.

I'm using iMX Platform SDK for my i.MX6 DualLite processor.

I'm trying to copy a large amounts of data from ethernet buffer to another. For this purpose I'm trying to use MMU with L1 cache.But I have a problem.

When I use Write-through cache the memcpy() function shows the tranfer rate is equal to 20MByte/s. It is not enough for my application.

When I use Write-back cache (rate is 150MByte/s) the ENET driver does not work. I think this is due to lack of data coherency among DDR memory and L1 data cache and I don't know how to fix it.

In my application I'm trying to encode real time video (captured from the ethernet) but I dont have time to copy data from ENET buffer to VPU buffer.

I have some questions.

 

1. What is the typical tranfer rate for IMXDL processor?

2. How to achieve the maximum data rate among 1Kbytes memory blocks that are located in the area which can be changed using DMA ? (e.g. ENET buffer). Write-back cache provides the desired performance (50MByte/s) but it does not work DMA.

3. How can I achieve data coherency with write-back memory model?

 

4. Can the problem with ENET being in another?

5. If there are any errors in my platform_init() function and memory settings (listed below)?

 

Thanks in advance.

 

ARM clock is 996MHz

DDR3 with Data Rate 1600 MT/s.

 

I'm using default platform_init() function from iMX SDK with small changes.

void platform_init(void)
{
    enable_neon_fpu();
    disable_strict_align_check();
    mmu_init();

    arm_icache_enable();
    arm_dcache_invalidate();
    mmu_enable();
    arm_dcache_enable();

    // Enable interrupts
    gic_init();
    arm_set_interrupt_state(true);
    
    // Initialize clock sources, dividers, ... 
    ccm_init();
    
    // Configure the EPIT timer used for system delay function. 
    system_time_init();
}

 

MMU mappings.

//                physical     virtual     length
mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
mmu_map_l1_range(0x10000000, 0x10000000, 0x30000000, kOuterInner_WB_WA, kShareable, kRWAccess); 

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