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Regarding i.MX6DQ LDB clock (unexpected frequency was output).

Question asked by Satoshi Shimoda on Nov 25, 2015
Latest reply on Nov 27, 2015 by igorpadykov

Hi community,

 

I have a question about i.MX6DQ LDB clock.

Please see my question as blow.

 

[Q1]

Please see Figure 18-8 (page.824) in IMX6DQRM.

I believe LDB_DIx_SERIAL_CLK_ROOT is used for DIx_SERIAL_CLK in Table 39-4, and ldb_dix_ipu is used for IPU_DIx_CLK.

Is this correct?

 

[Q2]

I believe LVDS clock output from LVDSx_CLK_P/LVDSx_CLK_N pad is DIx_SERIAL_CLK = LDB_DIx_SERIAL_CLK_ROOT, right?

 

[Q3]

Actually, LVDS1_P clock frequency was about 75.4MHz when our partner measured it even though all CCM register set to PLL2 = MMDC_CH1_AXI_CLK_ROOT = LDB_DI1_CLK_ROOT.

It seems to be 528/7 MHz, and it seems to be ldb_di1_ipu.

Would you give me some adivise why 75.4MHz (528/7MHz?) is output from LVDS1_CLK_P?

 

 

Best Regards,

Satoshi Shimoda

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