We are using the mainline kernel for i.MX535 and the driver for it (i2c-imx.c). We are using the i2c to read 2 bytes from a device (a simple sensor).
The driver works in such a way that each time data is written or read to/from the I2C_I2DR register it waits for the interrupt handler to receive and clear the IIF bit in the I2C_I2SR register. The interrupt handler notifies the driver to continue (reading/writing another byte). The DMA is not used.
The problem is that if there is too much time spent on CPU being busy between clearing of the IIF bit and reading the next byte from the I2DR register, the register's contents are 0xFF (I.e. wrong). In cases where the register is read quicker, the contents are proper.
Is there some limitation in hardware on how long the value stays in the I2DR register after the IIF has been cleared ?