// Enable interrupt for when transmission of single byte is completeMCF_UART_UIMR0 |= MCF_UART_UIMR_TXRDY;
On page 13-8 of the Rev. 1.1 and Rev. 2.0 manuals (MCF5235RM/D) is the following note:
NOTEIf an interrupt source is being masked in the interrupt controller maskregister (IMR) or a module’s interrupt mask register while theinterrupt mask in the status register (SR[I]) is set to a value lower thanthe interrupt’s level, a spurious interrupt may occur. This is because bythe time the status register acknowledges this interrupt, the interrupthas been masked. A spurious interrupt is generated because the CPUcannot determine the interrupt source. To avoid this situation forinterrupts sources with levels 1-6, first write a higher level interruptmask to the status register, before setting the mask in the IMR or themodule’s interrupt mask register. After the mask is set, return theinterrupt mask in the status register to its previous value. Since level 7interrupts cannot be disabled in the status register prior to masking,use of the IMR or module interrupt mask registers to disable level 7interrupts is not recommended.
What I don't understand is the statement about "first write a higher level interrupt mask to the status register". Which register is this referring to? I cannot find any registers that implement an interrupt level except for the ICR[nx] registers, but this does not seem to be what is talked about here.
Is there some clarification about how to do this?