MC1321x Single port transmission problem

[swe]

Hi,

I am trying to transmit data (packet mode) from a PAN4555_ETU which uses single port RF configuration. But every time the transmit routine is called, it causes PLL_LOCK_IRQ and aborts transmission process. The same code is sucessfully tested in 1321x-SRB, but configured in duel-port RF mode (CONTROL_B, RF_SWITCH_MODE=0).

In my test board, the PAN4555_ETU is mounted on a 28PIN DIP IC socket and the VCC and VDDA pins are grounded across 100nF caps (the borad is powered from 2 AAA batteries). The test board is hand soldered. As I read on freescale forums and other sources, the PLL_LOCK_IRQ is generated due to the noise in the circuit. However, in an off-the-shelf modules like PAN4555_ETU, I hope, the noise problem would not be an issue.

I just wonder if any one has come through such problem using PAN4555 or generally MC1321x. I could not move further in my project due to this, any help in this matter would be highly appriciated. Thanks in advance.

swe

[Ware]

I am also using the PAN4555.

On the PAN4555_ETU make sure pin 27 (Vdda) is connected to bypass cap (but NOT connected to Vcc!) see attached image.

I also had single-port issues... (see http://forums.freescale.com/freescale/board/message?board.id=8BITCOMM&message.id=6780#M6780 ).  But eventually worked through them.

edit the FILE: "Mc1319xReg.h" (lines 141-143)

Code:

/**  Register 0x07 aka ABEL_CONTROL2_REG*/#define ABEL_CONTROL2_REG ABEL_reg7#define cTMR_LOAD       (1<<15)#define cCT_BiasEn      (1<<14)#define cRF_SwitchMode  (1<<12)#define cCLKO_DOZE_EN   (1<<9)#define cABEL2SPI_MASK  (1<<8)#define cTX_DONE_MASK   (1<<7)#define cRX_DONE_MASK   (1<<6)#define cUSE_STRM_MODE  (1<<5)#define cHG_BIAS_EN     (1<<4)#define cHG_EN          (1<<2)#define cHIB_EN         (1<<1)#define cDOZE_EN        (1<<0)

 

- Then modify "MacPhy\Phy\PhyMain.c" (lines 170-177)

Code:

    // Setup default antenna switch mode  if (useDualAntenna == TRUE){    MC1319xDrv_ReadSpiAsync(ABEL_CONTROL2_REG, &retReg);    retReg &= 0x8FFF;    retReg |= 0x4000; // Dual antenna setup at boot, CT_Bias_en = 1, RF_switch_mode = 0, CT_Bias_inv = 0    MC1319xDrv_WriteSpiAsync(ABEL_CONTROL2_REG, retReg);  }  else   {   // Single antenna setup at boot, CT_Bias_en = 1, RF_switch_mode = 1, CT_Bias_inv = 0    MC1319xDrv_ReadSpiAsync(ABEL_CONTROL2_REG, &retReg);    retReg &= 0x8FFF;    retReg |= ((uint16_t)cCT_BiasEn | (uint16_t)cRF_SwitchMode);    MC1319xDrv_WriteSpiAsync(ABEL_CONTROL2_REG, retReg);  }

- Lastly, check lines 153-159 of "NV_Data.c" and line 167 of "PortConfig.h" to ensure "useDualAntenna" is defined as FALSE 

NOTE: My "PhyMain.c" mod could be re-writen/optimized (I purposely left it like this to help people find the original code).

NOTE 2:  When Freescale updates their BeeStack codebase in BeeKit, this may not apply.

Regards,

 - Ware

[swe]

Thank you Ware,

In my circuit VDDA (PIN27) is connected with VCC and then connected to GND via a 100nF cap.

I will remove the VCC connection and try again. Will let you know the outcome soon.

Why do you think that the VDDA and VCC should not be connected? (Is that a requirement for single-port mode or in PAN4555)

Thanks again for your reply.

SWE

[Ware]

I'm glad we found your problem.  I made the same mistake a few months back.

Vdda must NOT be connected to Vcc (Vdda is not an input, it is the radio's voltage output, only brought out so that it can be DECOUPLED to ground).

It should be around 1.5v out...  if it is shorted to 3v (your Vcc), you are shorting the radio's 1.5v output to 3v, which will prevent the radio from working.

This is NOT a requirement for single-port mode, this is a requirement for the 802.15.4 radio to work.

See the Pin Function Description table in the MC1321x reference manual.

Regards,
 - Ware

Message Edited by Ware on 2008-01-21 09:48 AM

[swe]

Hi Ware,

I just finished testing the system sucessfully with the modification to the VDDA pin that you suggested. Thanks a lot for the advice.

Best Regards,

SWE