The P1010 Errata A-004508 states that bit 22 of a register at location 0x0_2f08 offset from the CCSR should be set if the controller is initialized below 0 degrees C and then operated at temperatures above 65 degrees C.
The P1010 Reference Manual has no definition of the register at 0x02f08 off the CCSR. The largest offset for a DDR related register is at 0x02E58 (DDR_ERR_SBE).
When reading the mystery register I usually see 0x00000010, but occasionally I read 0x00000011.
Does anyone have a definition of the bits in this register (CCSR + 0x02f08)? If I perform a read/modify/write to set bit 22 in this register will it cause any issues (even if the LSB is set)?
Note: P1010 Chip Errata, Rev. L, 04/2013