P2020 DMA won't burst over PCIE!?

[nickangelo]

We are using the P2020 CPU along with several FPGAs on one of our boards. For the last 2 weeks we have been trying to get the P2020 DMA engine to burst data over the PCIE to a Xilinx Virtex 7 FPGA. I have scoped the signals in the FPGA and verified that the DMA is sending only 1 word payloads in each TLP which is very inefficient. We have checked the BWC register and it's set to 8. The DMA transfer size is set to 1024 bytes. How do we enable the DMA to burst at least 128 bytes per TLP? Is there any example code that sets up the DMA and PCIE controllers for such transfers? We suspect the P2020 configuration is wrong, but have no idea where else to look?

Thanks,
Nick

[LPP]

Please check the value of DMAx_MRn[DAHE,SAHE] (RM Section 13.3.1).

Probably, you are trying to DMA data to FPGA register on the PCIe side of DMA. DMA doesn't burst if DAHE,SAHE != 0.

The source/destination transaction size calculations provided in RM Section 13.4.1.1 is only applicable to the case of DAHE,SAHE = 0.

Have a great day,
Pavel

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------