I'm am trying to maximize flash execution performance (which is until now 30% lower than from internal SRAM with FMC Cache activated!).
AN4745 lists the following procedure on activating the LMEM cache:
1. Modify the cache region configuration in the LMEM_PCCRMR from the default values if desired.
2. Set the LMEM_PCCCR[INVW1 and INVW0] bits to configure the controller to invalidate both ways of the CODE bus
3. Set the LMEM_PCCCR[GO] bit to start the invalidate.
4. Wait for the LMEM_PCCCR[GO] bit to clear indicating the command has completed.
5. Enable the CODE bus cache by setting LMEM_PCCR[ENCACHE].
6. Set the LMEM_PSCCR[INVW1 and INVW0] bits to configure the controller to invalidate both ways of the system bus
7. Set the LMEM_PCCCR[GO] bit to start the invalidate.
8. Wait for the LMEM_PSCCR[GO] bit to clear indicating the command has completed.
9. Enable the system bus cache by setting LMEM_PSCR[ENCACHE].
But unfortunately, I can't find any sign of existence for the registers LMEM_PSCR and LMEM_PSCCR in K65.
Am I missing something?
Seems like these registers are only available in Kinetis K70 devices since only these have the SYSTEM cache controller.
What does this missing cache controller mean for the flashe execution performance of the K65 devices ?#
I also found out, that enabling the cache in some cases reduces the flash execution performance so simply enabling it may slow down the application.
Is there a special Application Note regarding cache best practices on freescale?