Hi, I'm trying to configure the IMX6Q as a PCIe endpoint. It's hooked up to another board which is the root complex. I'm using the Freescale bare metal SDK PCIe test as a starting point. I'm calling pcie_init() with the parameter PCIE_DM_MODE_EP instead of PCIE_DM_MODE_RC. At this point the link will not come up. I have a JTAG debugger hooked up and it seems like the CPU get stuck in the wait_link_up() function - it gets inside there and then the debugger is no longer able to halt the core. If I set breakpoints and single step through wait_link_up(), it goes through OK but the link never succeeds. Any ideas? Is there code anywhere for the bare metal SDK to configure the PCIe as an endpoint instead of a root complex?
Solved! Go to Solution.
Thanks, Norbel suggested we enable the 100MHz SATA clock in the ethernet PLL and that seems to have fixed the issue. Now I need to figure out how to configure registers via DBI, I will post another thread about that.
HI Elijah
please look at
i.MX6Q PCIe EP/RC Validation System
Best regards
igor
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Thanks, Norbel suggested we enable the 100MHz SATA clock in the ethernet PLL and that seems to have fixed the issue. Now I need to figure out how to configure registers via DBI, I will post another thread about that.