I am trying to generate a Boundary scan test vector with the Cascon JTAG tool from Göepel for an i.MX6S based board.
The test failed at the checking boundary scan register test if we use the test byte.
The test was able to read the IDCODE, so the communication with the chip should be ok.
This test step is basically loads the SAMPLE/PRELOAD instruction to IR, and then shifting out a pattern to the BSR (through DR) prefixed with an extra test byte.
The test byte should be read back on TDO after shifting the correct number of bits to the BSR (since it is a shift register), but it won't appear.
Further investigation with a logic analyzer shown that when clocking the DR in SAMPLE mode the TDO output is always stays at zero.
First I have suspected the BSDL file BSR section, but with EXTEST mode I can toggle the last pin (CSI0_DAT19) and one of the first ones (BOOT_MODE1) too.
Any help would be deeply appericiated!