About Boot mode sampling timing in i.MX6DQ.

[keitanagashima]

Dear All,

Hello.

I have a question about Boot mode sampling timing in i.MX6DQ.

I found the below 3 descriptions.

========

1. Refer to the 60.6.1.2.3 POR (SRC_POR_B) in IMX6DQRM(Rev.2)  - page.5056.

"Once the above resets deassert, system_early_rst_b reset is deasserted after 2 XTALI clocks."

2. Refer to 60.6.1.2.4 COLD RESET in IMX6DQRM(Rev.2)  - page.5056.

"Once the reset source deasserts, system_early_rst_b reset is deasserted after at least 2 XTALI clocks."

3. Refer to the 59.4.4.1 BMOD Pin Latching in IMX6DQRM(Rev.0)  - page.5008.

"All the boot pins will be sampled at deassertion of system_early_rst_b."

========

So, I understood that All the boot pins will be sampled after at least 2 XTALI clocks from POR_B.

[Question]

How much is it necessary to keep the logic of Boot Mode Configuration Pins?

(Best case : 2XTALI clocks. Worst case : ?? clocks)

Best Regards,

Keita

[Yuri]

  The boot pins are latched at POR rising edge, but - strictly speaking -

the hold time  is not specified. Please look at sheet 13 of the i.MX6 SL EVK

design, where bus isolation buffer is applied and the next note is provided :

"i.MX6SL reads values approximately 300uS to 1mS after reset released.

Buffers are active while unit is in reset and 1ms-10ms after reset is released."

https://www.freescale.com/webapp/Download?colCode=iMX6SL_EVK_DESIGNFILES&appType=license&location=nu...

Have a great day,
Yuri

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[keitanagashima]

Hi Yuri,

Thank you for your reply.

[Q1]

Can this description be adaptable to i.MX6DQ, too?

[Q2]

What meaning of "unit is in reset"?

[Q3]

Should I keep the logic of Boot Mode Configuration Pins more long than at least 1 mS after reset released?

Best regards,

Keita

[Yuri]

Please look at my comments below.

1.

> Can this description be adaptable to i.MX6DQ, too?

Yes - in order to be fully on safeside.

2.
> What meaning of "unit is in reset"?

While POR is asserted.

3.
> Should I keep the logic of Boot Mode Configuration Pins more long than

> at least 1 mS after reset released?

I do not think so.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

Sorry. I couldn't understand well about below answer #3.

>3.

>> Should I keep the logic of Boot Mode Configuration Pins more long than

>> at least 1 mS after reset released?

>I do not think so.

I send you the below question again.

How long does it necessary to keep the logic of Boot Mode Configuration Pins after reset released?

Best Regards,

Keita

[Yuri · Accepted solution]

The value of 1.1 ms is good.

Regartds,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

OK. I got it.

Best Regards,

Keita