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About Boot mode sampling timing in i.MX6DQ.

Question asked by Keita Nagashima on May 6, 2015
Latest reply on May 10, 2015 by Keita Nagashima

Dear All,

 

Hello.

I have a question about Boot mode sampling timing in i.MX6DQ.

I found the below 3 descriptions.

 

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1. Refer to the 60.6.1.2.3 POR (SRC_POR_B) in IMX6DQRM(Rev.2)  - page.5056.

"Once the above resets deassert, system_early_rst_b reset is deasserted after 2 XTALI clocks."

 

2. Refer to 60.6.1.2.4 COLD RESET in IMX6DQRM(Rev.2)  - page.5056.

"Once the reset source deasserts, system_early_rst_b reset is deasserted after at least 2 XTALI clocks."

3. Refer to the 59.4.4.1 BMOD Pin Latching in IMX6DQRM(Rev.0)  - page.5008.

"All the boot pins will be sampled at deassertion of system_early_rst_b."

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So, I understood that All the boot pins will be sampled after at least 2 XTALI clocks from POR_B.

 

[Question]

How much is it necessary to keep the logic of Boot Mode Configuration Pins?

(Best case : 2XTALI clocks. Worst case : ?? clocks)

 

Best Regards,

Keita

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