I have a question about Boot mode sampling timing in i.MX6DQ.
I found the below 3 descriptions.
1. Refer to the 220.127.116.11.3 POR (SRC_POR_B) in IMX6DQRM(Rev.2) - page.5056.
"Once the above resets deassert, system_early_rst_b reset is deasserted after 2 XTALI clocks."
2. Refer to 18.104.22.168.4 COLD RESET in IMX6DQRM(Rev.2) - page.5056.
"Once the reset source deasserts, system_early_rst_b reset is deasserted after at least 2 XTALI clocks."
3. Refer to the 22.214.171.124 BMOD Pin Latching in IMX6DQRM(Rev.0) - page.5008.
"All the boot pins will be sampled at deassertion of system_early_rst_b."
So, I understood that All the boot pins will be sampled after at least 2 XTALI clocks from POR_B.
How much is it necessary to keep the logic of Boot Mode Configuration Pins?
(Best case : 2XTALI clocks. Worst case : ?? clocks)