Barry Upshaw

CPLD problem with M54455EVB

Discussion created by Barry Upshaw on Nov 9, 2007
Latest reply on Nov 11, 2007 by Barry Upshaw
I just received my M54455EVB and am having a problem accessing the CPLD as described in the User's Manual.  I'm using a simple "Hello World" console app. test for this.  I can access the FPGA registers at 0x0900_0000 as described in the manual (getting the expected values), but get only 0xFF for the entire mapped range for the CPLD (0x0800_0000).  The M54455EVB_RAM.cfg file contents are actually getting written to the CS registers (verified by a Register dump), as expected (see below).  I'm not sure the values are correct for the CPLD mode register (the manual says it should have BYTE access only).
Can anyone out there with an EVB try to perform a read from the CPLD registers and see if the results are as expected (i.e. something other than 0xFF)?
Is it possible to get access to the CPLD sources (I'm quite fluent at Xilinx builds)?
;Init CS2 - CPLD @ 0x0800_0000
writemem.l 0xFC008018 0x08000000;
writemem.l 0xFC008020 0x00000000;
writemem.l 0xFC00801C 0x00000001;
;Init CS3 - FPGA @ 0x0900_0000
writemem.l 0xFC008024 0x09000000;
writemem.l 0xFC00802C 0x00000020;
writemem.l 0xFC008028 0x00000001;