Our partner found a issue about i.MX6S eCSPI.
Actually, it seems that i.MX6S eCSPI trashes FIFO data if spike noise is input to SCLK when SS signal is negated.
If two spike noises are input to SCLK, two FIFO data seems to be trashed.
We think i.MX6S should not trash FIFO data even if spike noise or clock is input when SS signal is nageted.
So would you let me us why this issue is caused and how to avoid?