We have developed a software on an MPC5675K which works quite well when only one e200 core (the first) is active:
- both CTU units triggers at 10kHz the four ADC units, which write in two CTU FIFO, in turn emptied into SRAM by both DMA controllers
- the Coherency Unit and the DMA are configured to update the first core data cache
But when the MMU and data cache of the second core are configured together with the Coherency Unit - even when the second core execution is suspended by a "wait" instruction - the DADDR field of one of the DMA channels increments by the value of the its DOFF field every few minutes, slowly corrupting the SRAM as a consequence.
As if one DMA transfer was aborted and retried every now and then, but without first restoring the DADDR field to its previous value...