After applying the interlaced mode patches posted at Patch for iMX6 BSP to support interlaced display on HDMI and LCD interface, I've encountered issues while trying to perform HDMI compliance testing for interlaced modes. The first issue appears to be with the 4th patch. With the 4th patch applied the HDMI output will generate an invalid field every other field. It appears that one of the lines is cut short at the end of the field. Once this patch is reverted the remaining issue appears to be that the H to V offset is invalid. When operating in 1080i@60 we get an H to V value of 1101 and 1 depending on the field. These should be 1100 and 0 since the VSYNC should happen during the same clock cycle as the HSYNC. I've tried manipulating various parameters of the IPU timing generation signals but havent found a way to correct the H to V offset. Any ideas?