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i.MX6SDL eCSPI behavior in slave mode.

Question asked by Satoshi Shimoda on Dec 25, 2014
Latest reply on Mar 10, 2015 by igorpadykov

Hi community,

 

We want to confirm about i.MX6SDL eCSPI behavior.

Please see our questions as below.

 

[Q1]

Please see chapter 21.7.5 in IMX6SDLRM (Rev.1).

In slave mode when SS_CTL=0, we guess i.MX6SDL eCSPI does NOT input/output data if SS signal is negated.

Is this correct?

Or SS signal is ignored and i.MX6SDL inputs/outputs with only SPI clock even if SS signal is negated?

 

 

[Q2]

In slave mode when SS_CTL=1, we understand RXFIFO is advanced whenever a SS signal edge that shows burst complete, and RXFIFO is NOT advanced whenever a SS signal edge that shows burst start.

Is this correct?

And then, how about TXFIFO?

Is TXFIFO advanced at the same time as RXFIFO? or is TXFIFO not advanced by SS signal edge?

 

 

Best Regards,

Satoshi Shimoda

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