a problem about hdmi and BT.656 display on one ipu

[wangzhigang]

hi,

I patch the file(Patch to Support BT656 and BT1120 Output For i.MX6 BSP),and I have a problem for display hdmi and BT.656 in one ipu.

1.(hdmi in ipu2,Bt.656 in ipu1)

bootargs:

video=mxcfb0:off  video=mxcfb1:dev=bt656,BT656-PAL,if=BT656,bpp=32 video=mxcfb2:dev=hdmi,1028x720M@60,if=RGB24,bpp=32 fb0base=0x27b00000

board_mx6q_sabresd.c

static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {

    .ipu_id = 1,

    .disp_id = 1,

};

static struct fsl_mxc_lcd_platform_data lcdif_data = {

    .ipu_id = 0,

    .disp_id = 0,

    .default_ifmt = IPU_PIX_FMT_RGB565,

};

static struct fsl_mxc_ldb_platform_data ldb_data = {

    .ipu_id = 0,

    .disp_id = 0,

    .ext_ref = 1,

    .mode = LDB_SEP1,

    .sec_ipu_id = 0,

    .sec_disp_id = 0,

};

static struct fsl_mxc_lcd_platform_data bt656_data = {

    .ipu_id = 0,

    .disp_id = 0,

    .default_ifmt = IPU_PIX_FMT_BT656,

};

HDMI is almost OK,but the colour of display is more red than normal.

BT.656 may be OK,because we have not hardware to conform,we just test the signal,every signal is OK.

2.(hdmi in ipu1,BT.656 in ipu1)

I just change the hdmi's parameter as follow:

static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {

    .ipu_id = 0,

     .disp_id = 1,

};

HDMI can not display,I test the hdmi's clk,It's OK.and BT.656 still have signal.

and the displayer on hdmi say that "不能显示此视频模式，请将电脑重新设置为XXXXX" when hdmi and BT.656 in the same ipu.

Could you tell me how to display hdmi and BT.656 in one IPU,because we have to use the other ipu for ldb in split mode?I just change the parameter in board_mx6q_sabresd.c.

please help me!!

Best Regards.

            wangzg

[qiang_li-mpu_se]

Please double check the arch\arm\mach-mx6\clock.c:

For BT656 output on ipu_id=0, disp_id=0, it should be:

clk_set_parent(&ipu1_di_clk[0], &pll3_pfd_540M);  /* For CVBS 27MHz clock */

clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);

clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);

clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);

[wangzhigang]

hi,Qiang

I test again,the result is  as follow:

If the LVDS in ipu1,It's OK;LVDS in ipu2,the LVDS do not display.

If the LVDS in ipu1,and HDMI in ipu2(DP DI),both of them is OK.but if the HDMI in ipu2(DC DI) ,the HDMI do not display.

If the BT.656 in ipu1(DP DI),the clk of BT.656 is 27MHz,ifBT.656 in ipu2(DP DI or DC DI) ,the clk of BT.656 is 71.45MHz(abnormal).

My system want the LVDS in ipu1 (split mode),HDMI in ipu2(DC DI),BT.656 in ipu2(DP DI),but now the LVDS is OK,the HDMI in ipu2(DC DI)do not display,and the BT.656's clk is 71.45MHz,the follow is my code:

clock.c

//clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);

    clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);

    clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);

#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS

    //clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);

#endif

    clk_set_parent(&ipu2_di_clk[0], &pll3_pfd_540M); /* For CVBS 27MHz clock */

    clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);

board-mx6q_sabresd.c

static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {

    .ipu_id = 1,

    .disp_id = 1,

};

static struct fsl_mxc_lcd_platform_data lcdif_data = {

    .ipu_id = 0,

    .disp_id = 0,

    .default_ifmt = IPU_PIX_FMT_RGB565,

};

static struct fsl_mxc_ldb_platform_data ldb_data = {

    .ipu_id = 0,

    .disp_id = 1,

    .ext_ref = 1,

    .mode = LDB_SEP1,

    .sec_ipu_id = 0,

    .sec_disp_id = 1,

};

static struct fsl_mxc_lcd_platform_data bt656_data = {

    .ipu_id = 1,

    .disp_id = 0,

    .default_ifmt = IPU_PIX_FMT_BT656,

};

bootargs is :

video=mxcfb0:dev=ldb,PAD,if=RGB666,fbpix=RGB565,bpp=32 fbmem=64M,64M,64M ldb=dul0 video=mxcfb1:dev=bt656,BT656-PAL,if=BT656,bpp=16  fb0base=0x27b00000 video=mxcfb2:dev=hdmi,1028x720M@60,fbpix=RGB565

Is the BT.656 must in ipu1? and the LVDS must in ipu1 too?

Best Regards.

[qiang_li-mpu_se · Accepted solution]

The BT656 depends on your hardware pins used with the BT656 interface, they are fixed on IPU1 or IPU2 with the fixed hardware link.

[wangzhigang]

hi,Qiang

  I success to switch the bt656 interface in ipu2,the BT656 clk is OK,but I have another problem.

  if we use LVDS in ipu1,and hdmi in ipu2(DC D1),BT656 in ipu2(DP D0),the LVDS is OK,and BT656 is OK,but hdmi haven't display.

  if close LVDS,Both the bt656 and HDMI is ok.

  whether the LVDS'clk affect the HMDI'clk?

  do you have some ideas?

[wangzhigang]

hi,

Thanks for your replay.

Do you means that you fix the BT656 interface in ipu2? and how can I switch bt656 from ipu1 to ipu2.

[qiang_li-mpu_se]

The BT656 interface has 8 data pin and 1 clock pin, if your board had connected IPU1_DISP pins to the BT656 encoder chip, such as the adv7390, that means your hardware had fixed the BT656 interface to IPU1; if your board had connected IPU2_DISP pins to the BT656 encoder chip, that means your hardware had fixed the BT656 interface to IPU2.

[wangzhigang]

hi,Qiang

It is all ok,Thanks for your help.