AnsweredAssumed Answered

imx6 DDR_SEL

Question asked by Andrew Dyer on Oct 17, 2014
Latest reply on Oct 17, 2014 by Mark Middleton

In the i.MX6 reference manual [1] section 37.4.289 (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) it says the DDR_SEL field should be '11' for DDR3.  Value '00' is marked as reserved.


Looking at the code for DRAM setup u-boot from the Freescale git repository[2], it sets the bits to '00' (reserved).  I also see this as the recommended setting in the DDR3 setup spread sheet[3].  Which value for those bits is the correct one?

 

[1] i.MX 6Solo/6DualLite Applications Processor Reference Manual
Document Number: IMX6SDLRM Rev. 1, 04/2013

 

[2] uboot-imx.git - Freescale i.MX u-boot Tree

 

[3] I.MX6DQSDL DDR3 Script Aid V0.10 i.Mx6DQSDL DDR3 Script Aid

Outcomes