In the i.MX6 reference manual  section 37.4.289 (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) it says the DDR_SEL field should be '11' for DDR3. Value '00' is marked as reserved.
Looking at the code for DRAM setup u-boot from the Freescale git repository, it sets the bits to '00' (reserved). I also see this as the recommended setting in the DDR3 setup spread sheet. Which value for those bits is the correct one?
 i.MX 6Solo/6DualLite Applications Processor Reference Manual
Document Number: IMX6SDLRM Rev. 1, 04/2013
 I.MX6DQSDL DDR3 Script Aid V0.10 i.Mx6DQSDL DDR3 Script Aid