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IMX6Q L2 Cache TAG and RAM latency settings?

Question asked by Jon Watson on Jun 27, 2014
Latest reply on Jul 25, 2014 by gusarambula

In the IMX6 Quad technical reference manual I see that Table 12-5 “PL310 L2 Cache Configuration” (see pg 569 of the i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013), specifies “RAM   Latencies” as 4 and has a footnote that 4 is a preliminary value, final value is TBD.


What is the final value that should be used when setting the PL310 TAG RAM and DATA RAM latency control registers?