In the IMX6 Quad technical reference manual I see that Table 12-5 “PL310 L2 Cache Configuration” (see pg 569 of the i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013), specifies “RAM Latencies” as 4 and has a footnote that 4 is a preliminary value, final value is TBD.
What is the final value that should be used when setting the PL310 TAG RAM and DATA RAM latency control registers?
I apologize. I couldn’t locate this specific information but may I ask why do you need this parameter? Maybe we can help with some other information.
We’re investigating what the final figure should be. I’ll let you know as soon as we have an update.