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Why SPRF is never being set on SPI0 read for MKL25Z128VFT4?

Question asked by Bob Paddock on Jun 3, 2014
Latest reply on Jun 20, 2014 by Bob Paddock

I am having a problem getting SPI0, on PORTC, to work on a MKL25Z128VFT4 part.

 

The SPRF data ready flag is never getting set, causing my SPI read/write routine to lock up.

 

I'm tiring to use the simplest code possible, no DMA, Interrupts or frameworks.

 

The problem is that the SPRF data bit is never getting set in the status register.
This makes me fell I've missed something in clock initialization.

 

I have no external crystals, I want to run on the internal clocks (cost issue).

 

I have tried code produced by Code Warrior and also done no clock
initialization at all, just going with the defaults out of reset, and get
the same results.

 

SPI0 is clocked by the Bus Clock.  I do not see, or am constantly
overlooking, in the data sheet anything that indicates I need to
specifically enable the bus clock after a hardware reset.

 

There is no debugger running that would corrupt the status registers.

 

Code below, what am I missing?:

 

static void spi0_init( void );
static void spi0_init( void )
{
  SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;    /* Enable PORTC clock */
  SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK;     /* Enable SPI0 clock  */

 

#if 0 /* Slave Select control is not shown in this posting */
    PORTC_PCR4 = PORT_PCR_MUX( 2U );    /* Set PTC4 Pin Mux Control Alternative 2 [SPI0_PCS0] */
#endif

    PORTC_PCR5 = PORT_PCR_MUX( 2U );    /* Set PTC5 Pin Mux Control Alternative 2 [SPI0_SCK]  */
    PORTC_PCR6 = PORT_PCR_MUX( 2U );    /* Set PTC6 Pin Mux Control Alternative 2 [SPI0_MOSI] */
    PORTC_PCR7 = PORT_PCR_MUX( 2U );    /* Set PTC7 Pin Mux Control Alternative 2 [SPIO_MISO] */

 

    /* SPIE=0, SPE=0, SPTIE=0, MSTR=1, CPOL=0, CPHA=0, SSOE=0, LSBFE=0: */
    SPI0_C1 = SPI_C1_MSTR_MASK;                           /* Set SPI0 to Master */

 

    SPI0_BR = (SPI_BR_SPPR(0x07) | SPI_BR_SPR(0x08));       /* Set baud rate prescale divisor and baud rate divisor to the slowest frequency for testing */

 

    /* SPIE=0, SPE=1, SPTIE=0, MSTR=1, CPOL=0, CPHA=0, SSOE=0, LSBFE=0: */
    SPI0_C1 |= SPI_C1_SPE_MASK;                             /* Enable SPI0 */
}

 

static uint8_t spi0_tx_rx( uint8_t const spi_write_data_u8 );
static uint8_t spi0_tx_rx( uint8_t const spi_write_data_u8 )
{
  while( 0U == (SPI0_S & SPI_S_SPTEF_MASK) )            /* Wait for SPI transmit empty flag to set */
    {
      NOP();
    }

  SPI0_D = spi_write_data_u8;                           /* Write data to SPI */
  /* By toggling a pin it is known we *DO* get here */

 

  while( 0U == (SPI0_S & SPI_S_SPRF_MASK) )             /* Wait for receive flag to set */
    {
      NOP();
    }
  /* By toggling a pin it is known we do *NOT* get here */

 

  uint8_t const spi_read_data_u8 = SPI0_D; /* Read the SPI data register, with SPRF set, above, this will clear SPRF */
  return( spi_read_data_u8 );
}

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