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PWM Duty Cycle Issue - Kinetis L ( MKL26Z128 )

Question asked by Jan Kapic on May 23, 2014
Latest reply on Oct 1, 2018 by Mark Butcher

Hi Everyone!


I want to use TPM2 timer (Edge-Aligned PWM Mode) as DAC for audio generating. The reason for this solution is that I need more than one channel for my application (simple Wave player and tone generator).


I need at least two channels and I haven't been able to successfully multiplex output of DAC (there is only one channel in MKL26Z128).




I've written easy app for generating sine wave with dev kit FRDM-KL25Z (very similar processor). In this application I'm using two timers TPM1 and TPM2:


- TPM1 is used for PWM duty cycle changing with sampling frequency 8 KHz.

- TPM2 is used in Edge-Aligned PWM Mode, counting with frequency c. 93 Khz.

Everything works fine except one state. When I want to set CnV ( PWM compare register ) with value 1, there is unexpected glitch in PWM duty cycle.

PWM duty cycle should be close to 0%, but sometimes instead of 0%, there is PWM duty cycle 100%.

The result of this glitch is shown in figure below.


Also I've attached whole project, where I'm generating sine wave.

In combination with PWM I'm using R C low pass filter (R = 10k, C = 100n). Output of PWM is on pins PTE23 and PTE22.


Are there any rules, for setting TPMx_CnV register? What am I doing wrong?


Ugly, but simple solution to this is instead of 1 set CnV with value 2, but I don't really want this.





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