I have a custom board with iMX6 quad-core, designed starting from SabreSD.
Most of these boards correctly boot with the ddr clock at 528MHz (the default value used in the eval board); however, some boards don't boot.
I started assuming that the ddr clock is too high and I modified the DCD-table (flash-header.S) in order to configure the ddr controller to operate at 396MHz.
With a jtag emulator, if I configure the ddr controller with the same values used in the new DCD-table then I am able to read, change and write the ddr memory with no problem.
If I download the new u-boot (builded with the new DCD-table) in my board, the system don't start...
The ddr memory is now clocked at 396MHz, but if I stop the execution, with the jtag, I see that the core is executing code placed at very low addresses; this meas (I suppose) that the core is still running the ROM code and u-boot is not started.
thank you very much!!