DDR: Clock Slow-down on i.MX6Q Sabre SDB-P boards

Document created by Leonardo Sandoval Gonzalez Employee on Nov 21, 2013Last modified by ebiz_ws_prod on Dec 13, 2017
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The attached patches slow-down the DDR's clock (from 528000000Hz to 396000000Hz) on i.MX6Q Sabre SDB-P boards. These were tested on Android JB4.2.2_1.0.0 and Linux L3.0.35_4.1.0.


To verify patches were correctly applied, one the serial console one should see the following TWO bold lines



Board: i.MX6Q-SABRESD: unknown-board Board: 0x63012 [POR ]

Boot Device: MMC

I2C:   ready

DRAM:   1 GB


*** Warning - bad CRC or MMC, using default environment


mx6q pll1: 792MHz

mx6q pll2: 528MHz

mx6q pll3: 480MHz

mx6q pll8: 50MHz

ipg clock     : 49500000Hz

ipg per clock : 49500000Hz

uart clock    : 80000000Hz

cspi clock    : 60000000Hz

ahb clock     : 99000000Hz

axi clock   : 198000000Hz

emi_slow clock: 99000000Hz

ddr clock     : 396000000Hz

usdhc1 clock  : 198000000Hz

usdhc2 clock  : 198000000Hz

usdhc3 clock  : 198000000Hz

usdhc4 clock  : 198000000Hz

nfc clock     : 24000000Hz

In:    serial

Out:   serial

Err:   serial

Found PFUZE100! deviceid=10,revid=10

Net:   got MAC address from IIM: 00:04:9f:02:67:46


Hit any key to stop autoboot:  0

kernel   @ 10808000 (4709060)

ramdisk  @ 11800000 (183100)

kernel cmdline:

    use boot.img command line:

    console=ttymxc0,115200 init=/init video=mxcfb0:dev=ldb,bpp=32 video=mxcfb1:off video=mxcfb2:off fbmem=10M fb0base=0x27b00000 vmalloc=400M androidboot.console=ttymxc0 androidboot.hardware=freescale


Starting kernel ...


Uncompressing Linux... done, booting the kernel.




sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms

Set periph_clk's parent to pll2_pfd_400!





Original Attachment has been moved to: 0001-kernel-DDR-slow-down.patch.zip

Original Attachment has been moved to: 0001-u-boot-DDR-slow-down.patch.zip

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