AnsweredAssumed Answered

i.MX280 processor resetting when EMI or CPU clock is taken out of bypass

Question asked by Matt Brandt on Apr 17, 2014
Latest reply on Jul 23, 2014 by ramesh nair

I am debugging a custom i.MX280 board based on the evk design. We are having a problem getting through the SPL because the processor usually resets shortly after the EMI clock is taken out of bypass. Sometimes, though, it stays stable enough to go through the memory init and get into the CPU and HBUS setup where the cpu clock is configured but it always fails soon after hw_clkctrl_cpu is written to take the cpu clock out of bypass. It seemed to behave slightly better when I slowed down the EMI clock by 2X (divide by 4 instead of 2), but that might be a red herring.


We suspect this is a PMIC configuration problem since we don't have a battery on our board. Instead we have BATTERY and DCDC_BATT tied to VDD4P2 on the processor through 1K resistors as shown in AN4199.


I am using u-boot SPL booting from an SD card. In the PMIC configuration I tried clearing EN_BATADJ and PWDN_BATTBRNOUT and set BRWNOUT_PWD at the end of the brownout detect initialization, but this does not seem to help.


What am I missing?