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When does ADC sample time actually start?

Question asked by R. Steve McKown on Apr 11, 2014
Latest reply on Apr 14, 2014 by Perla Andrea Moncada Fajardo

Hi all,


I'm hoping someone can provide definitive clarity about how the ADCx peripherals work on K SF3 devices, specifically as it relates to computing sample time.


I've implemented a working variant of AN5940 to implement multi-channel streaming ADC capture on several different Kinetis K SF3 devices (K60FX512VLQ12 is one).  It works like PDB -> ADC -> DMA


Per the Reference Manual, I believe in this configuration, conversion starts in the ADC at the rising edge of the hardware trigger generated by the PDB.  And, this 'conversion' includes both sample time and conversion time, in the strict sense of the two terms.


For a SAR converter, sample time actually starts when the input signal is gated to the converter.  Of course sample time is provided to allow the input capacitance of the converter to stabilize within 1/2 LSB of the input signal before actual SAR conversion beings.


What is not clear to me is when the input signal is actually gated into the ADC.  Is it:


1. When the DMA writes the new channel to ADC0_SC1A, or

2. when the ADC receives the hardware trigger from the PDB?


Thanks in advance, and sorry for the long message.