Hi,
I use Debug mode of WDOG, but WDOG timer does not stop evenif I set WDBG.
I set a register of WDOG in the following procedure.
①WDOG timer start:WDOG_WCR=0x3F34
②Suspend the watchdog timer(Debug mode):WDOG_WCR=0x3F32 or 0x3F36
※WDOG_WCR regster read is WDOG_WCR[WDBG] = 0.
Q1)Is this setting procedure right?
Q2)Please give me a sample program of the WDOG setting.
Best regards,
soichi
Solved! Go to Solution.
Hi
In Reference Manual there is a mismatch in section 26.6.1 Watchdog Control Register (WDOG_WCR) between the table and the graphic for WCR register
Dismiss the graphic. Table provides the correct information.
Besides that, I think your code is fine for a timeout around 32s
However take into consideration that the power-down counter is not affected by debug mode entry/exit.
For example, check next code
void wdbg_test()
{
reset_occurred = 0;
interrupt_handlers[128]= INTR_ROUTINE; // reset_occurred will be set inside this routine
SRC.SICR.B.WDOG_RST = 0x01; //Configure WDOGA5 reset as interrupt
// Starting WDOG debug mode test case
WDOGA5.WCR.R = 0x2736; //timeout 20s
printf("Start watchdog");
WDOGA5.WCR.B.WDE = 1;
printf("Wait here in debug mode for 20s... reset should not come");
//To continue: Manually disable the WDBG here
while(reset_occurred != 1); //Wait here for interrupt
}
I will try to check for a sample.
Meanwhile make sure you have the right address of the WDOG_BASE in the next file
\MVF50GS10MK50.h
Is wrongly pointing to 0x0, so you should remove that and add the correct base address as follows
#ifdef ARMCC_A5
#define WDOG_BASE (0x4003E000u)
#else /* M4 */
#define WDOG_BASE (0x4003F000u)
#endif
Hi,
Thank you for reply.
I use the following setting.
"#define WDOG_BASE (0x4003E000u)"
Sorry, Please try to consider it.
Best regards,
soichi
Hi
In Reference Manual there is a mismatch in section 26.6.1 Watchdog Control Register (WDOG_WCR) between the table and the graphic for WCR register
Dismiss the graphic. Table provides the correct information.
Besides that, I think your code is fine for a timeout around 32s
However take into consideration that the power-down counter is not affected by debug mode entry/exit.
For example, check next code
void wdbg_test()
{
reset_occurred = 0;
interrupt_handlers[128]= INTR_ROUTINE; // reset_occurred will be set inside this routine
SRC.SICR.B.WDOG_RST = 0x01; //Configure WDOGA5 reset as interrupt
// Starting WDOG debug mode test case
WDOGA5.WCR.R = 0x2736; //timeout 20s
printf("Start watchdog");
WDOGA5.WCR.B.WDE = 1;
printf("Wait here in debug mode for 20s... reset should not come");
//To continue: Manually disable the WDBG here
while(reset_occurred != 1); //Wait here for interrupt
}