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New KL25Z sample reset pin has 125KHz output

Question asked by Kai Liu on Mar 1, 2014
Latest reply on Mar 18, 2014 by Kai Liu

Because I can not connect my CMSIS-DAP to custom KL25Z boards, (Check this thread: which has brand new sample ordered via I probes the reset pin after getting suggestions from pgo


According to KL25P80M48SF0RM.pdf, $ External pin reset


This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode.


The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0. When this option selected, there could be a short period of contention during a POR ramp where the device drives the pin out low prior to establishing the setting of this option and releasing the RESET function on the pin.




I got the a wave from reset pin, about 125KHz, That means the KL25Z is always in reset pin.


Here come my questions:


  • Is it normal to a new sample?
  • Does it apply to KL only or all Kinetis (K+KL)?
  • How to solve it and download my code?



As a cross check, I post some screenshots from my LogicScope.



Fig 1: New KL25Z samples without connecting to SWD debugger


Fig 2: New KL25Z sample connecting to SWD debugger


Fig 3. New KL25Z trying to connect to SWD (There are three attepts to talk to the KL25Z on DIO/CLK, which keeps LOW for a while on DIO)


Fig 4. Zoom in A (CLK pulses)


Fig 5. Zoom in B


Fig 6. Zoom in C


Fig 7. Zoom in D


Fig 8. FRDM on board KL25Z erased disconnected to OpenSDA


Fig 9. FRDM on board KL25Z erased connected to OpenSDA


Fig 10. FRDM on board KL25Z programmed by OpenSDA