I have a question about the address phase of FLEXBUS.
(using MK20FN1M0VLQ12 of KInetis K series MCUs)
When I observed FLEXBUS with an oscilloscope, 2 cycles (bus clock) may be taken [ after an address bus and write enable changing ] for chip select to change.
By the catalog, it is 1cycle.
Please let me know the conditions used as 2cycle.