I have two questions about i.MX6SDL IPU display clock generation.
Please see my questions below.
Please see chapter 220.127.116.11 in IMX6SDLRM.
It says "The DI clock can be derived from IPU's clock (HSP_CLK) or from an external source (via the DIn_DISP_CLK - ipp_di_#_ext_clk pin)".
Next, please see chapter 38.5.194.
The discription explains about display clock generation only mede from HSP_CLK.
But I think I can generate display clock from external source by setting this field if I select external source by di0_clk_ext in chapter 38.5.193.
I want to confirm how to set the fractional part of dix_disp_clk_period in chapter 38.5.194.
I understand display clock will be" HSP_CLK / (1 + 1/16)" if I set dix_disp_clk_period = 0x011.
And it will be "HSP_CLK / (1+ 1/2)" if I set dix_disp_clk_period = 0x018.
Is my understanding correct?