for our application , we need to enable ECC in OCRAM and DDR3 and we use Vybrid Tower kit TWR-VF65GS10.
1) On-Chip Memory Controllers
In chapter 65 of Vybrid reference manual version 5 , it is written
"... The OCRAM_sys ECC function can be summarized in the following steps. Consider reads and writes
separately.
For data writes received by the OCRAM_sys memory controller:
• If enabled, the ECC logic generates the 8-bit checkbit field based on the 29-bit address + 64-bit data
• The 64 data bits + 8 checkbits are stored in the memory ...
&
Note standard ECC operation requires that the entire memory be written during system startup to
“initialize” correct checkbit values for all locations before read operations can be checked. To assist in this
process, the device implements two independent control flags for each OCRAM_sys controller: one that
enables checkbit generation on writes and another to enable checking on read operations. The memory
initialization writes can be performed directly by a processor or an appropriately configured DMA
channel."
When I am reading the paragrah above , it seem we need to enable and modify some register to activate the ECC but I have searched in reference Manual and I didn't find how initialize the controller to activate ECC
What is the process to enable the ECC on OCRAM ?
2) DDR3
I use the following procedure to enable ECC on DDR3
- I written the field ctrl-raw with value " ECC reporting is on, but no attempts to correct. or ECC reporting and correcting on" in register DDRMC_CR_57
- I set the field REDUC in register DDRMC_78
- I initialize the DDR3 with value 0xFFFFFFFF
- I enable the DDRMC interrupt to catch any issue
When I read the DDR3 memory with the following width32, 64, 128, 256 bits , it's OK
When I written the DDR3 memory with the following width 128, 256 bits , it's OK
but I written the DDR3 memory with the following width 32 or 64 bits , then the cortex A5 crashed and I need push the button reset
is that someone has already had this problem?
Thanks for any help
Regards
FRancois
(corrected)
Dear Francois,
Regarding the OCRAM ECC part of your request...
The below statements from our current Datasheet and Reference Manual:
as well as 'Figure 2-1. Detailed Block Diagram' and 'Table 2-2. Device Configuration', make it look like the ECC feature cannot be controlled.
At the same time, based on the older Reference Manual contents, it looks like that the ECC feature can be controlled. It is not fully clear yet why this information has been deleted, most likely based on assumption that this feature would be used quite rarely, if at all.
Work on the new Reference Manual is in progress, and possibly this information will be added into it. Since this information is considered "Confidential and Proprietary", until then, you will have to turn to our local FAE to download it from the Freescale internal thread Enabling Vybrid ECC on OCRAM.
Regards, Naoum Gitnik.
hi naoum
1)
In chapter 65 page 3468
"
The OCRAM_sys ECC function can be summarized in the following steps. Consider reads and writes separately.
For data writes received by the OCRAM_sys memory controller:
• If enabled, the ECC logic generates the 8-bit checkbit field based on the 29-bit address + 64-bit data
......
For data reads processed by the OCRAM_sys memory controller:
• The memory reads the addressed location returning 64 data bits + 8 checkbits
• If enabled, the ECC logic forms an 8-bit syndrome which is the XOR of the 8 checkbits read from
memory and the (re)calculated checkbits formed by passing the 64 data bits (plus the address field
checkbits) through the H-matrix logic. An all-zero syndrome indicates an error-free memory read,
else a memory corruption event has occurred."
For me , it 's written " If enable " , so we can disable ECC
2) If ECC is always enable then the boot rom should be initialiaze the OCRAM as describe in capter 65.1.
"Note standard ECC operation requires that the entire memory be written during system startup to
“initialize” correct checkbit values for all locations before read operations can be checked."
but it's seems the boot don't initialize the OCRAM and if after the boot my code Read the OCRAM , I don't have any ECC error
What is it the OCRAM ECC state after the boot ?
if enable , why we don't have any ECC error interrupt when we read this memory
If disable , how I enable the ECC ?
Hi Franois,
The default state for OCRAM ECC check is disabled. OCRAM ECC can be set in using on chip memory controller - not described in RM rev.5. Please wait for full description. We are working on it.
/Jiri
hi all
ECC OCRAM
We will wait the full version and we have contact our FAE to have this documentation Enabling Vybrid ECC on OCRAM.
ECC DDR3
About our issue with ECC on DDR3 describe in this discussion , Can someone help us understand the behavior ?
BR
francois
Hi Franois,
great - so now you have all necessary data for OCRAM I guess :smileyhappy:. Regarding SDRAM (DDR). I guess that you use CPU to init SDRAM memory. Please set DDRMC_CR058[ECC_DIS_WCRER] prior to fill the memory - more in RM chapter 34.6.5.1 Initialization of memory when using ECC.
/* Re-configure the DDR controller for an 8-bit port width */
reg32_write(DDR_CR078, 0x0000010c); // reduc = 1
/* Enable ECC - reporting and correcting on */
reg32_write(DDR_CR057, 0x03000000); // ctrl_raw = 11
/* Need to disable checking on partial writes to get test to pass */
reg32_write(DDR_CR058, 0x01000000);
/Jiri
hi
below I extract the code to initialize ECC on DDR3
.....
reg32_write(DDR_CR057, 0x03000000); // ctrl_raw
reg32_write(DDR_CR000, 0x00000601); // LPDDR2 or DDR3, start
i = 5000;
while (i--);
// ECC enable
// ctrl_raw, if DDR3, set 3, else 0
reg32_write(DDR_CR058, 0x01000000);
// init MEM
init_DDR3_ECC();
reg32_write(DDR_CR058, 0x00000000);
This procedure is OK . for initializing the DDR , we use the instruction STMIA r0!,{r1-r8}
After , I test the DDR with the following procedure
bl ca5_bench_read32 | |
bl ca5_bench_read64 | |
bl ca5_bench_read256 | |
bl ca5_bench_readOffset | |
bl ca5_bench_readfpu | |
bl ca5_bench_write32 | |
bl ca5_bench_write64 | |
bl ca5_bench_write256 | |
bl ca5_bench_writefpu |
the read procedure are OK , the write procedure ( ca5_bench_write256 & ca5_bench_writefpu ) are Ok , but the write procedure 32 & 64 bit crahed the board
If you need , I can send you the project or the sources files
Hi Francois,
before write using CPU you have to disable checking on partial writes. In your code you have it enabled back before write.
/Jiri
hi jiri
I join ddr.c file
At end of ddr_init2 function , you can see DDR3 initialization
//Disable the corruption. The ECC codes written to memory will match the new write data written to memory | |||||
reg32_write(DDR_CR058, 0x01000000); | |||||
// init DDR3 MEM | |||||
init_DDR3_ECC(); | |||||
// Allow the ECC codes for the entire user word to be corrupted. | |||||
reg32_write(DDR_CR058, 0x00000000); |
In file cortex_a5_test.s , you have assembler function that read and write the DDR3 and function that initialize the DDR3
When ECC is enable the following function work
init_DDR3_ECC
ca5_bench_read32
ca5_bench_read64
ca5_bench_read256
ca5_bench_readOffset
ca5_bench_readfpu
ca5_bench_write256
ca5_bench_writefpu
the following function fails and crash the board
ca5_bench_write32
ca5_bench_write64
if you see an error , please tell me , or do you have an example code that enable ECC on DDR3
Br
francois
hi jiri
When ECC is disable with interface to 8 bit ( field REDUC= 0) , all function assembler work
Br
francois
Hi Francois,
that is logical. in your code
.....
//Disable the corruption. The ECC codes written to memory will match the new write data written to memory | |||||
reg32_write(DDR_CR058, 0x01000000); | |||||
// init DDR3 MEM | |||||
init_DDR3_ECC(); | |||||
// Allow the ECC codes for the entire user word to be corrupted. | |||||
reg32_write(DDR_CR058, 0x00000000); |
now you write to memory
---------------------
please delete line reg32_write(DDR_CR058, 0x00000000)
you can also check attached code for ECC test.
/Jiri
hi jiri
In your ECC test , you use a memtest function .
Could you send me the source of this function , because I would like execute you ECC benchmark
Regards
francois
hi jiri
I found the issue about ECC in DDR3
When we initialize the DDR3 with the instruction that write 256 bit in DDR3 ( STMIA r0!,{r1-r9} ) then we cannot rewrite this DDR3 with instruction that write 32 or 64 bits
When we initialize the DDR3 with the instruction that write 32 bit in DDR3 ( STR r1, [r0] then it's OK
I modified your testbench ECC and I added a function ecc_32bits_test . in this function I added assembler function with the following code for you show the issue
ca5_bench_ecc_test
push {r3-r12,r14}
;init parameter
LDR r0,=ReadBase_ADDR
;init limit
LDR r2,=ReadLimit
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r10}
STMIA r0!,{r3-r6}
LDR r0,=ReadBase_ADDR
STMIA r0!,{r3-r4} ===========> this instruction crash the cortex A5 processor
LDR r0,=ReadBase_ADDR
LDMIA r0!,{r3}
Could you confirm this issue ?
because in this case , we cannot optimize the memset function or we forbidden the 256 instruction in our code when ECC is enable ?
francois
hi jiri
About ECC on OCRAM , I have another issue
- I have a program where the stack pointer is located in OCRAM . for performance issue , we have activate the MMU on this zone with the parameter Write_Back_Write_allocated, Shareable and we enable the data cache . When I run my program , we have an ecc error ( ECC interrupt) .
When I change the attribute Write_Back_Write_allocated, Shareable by Non-Cacheable , we have always error
When I change the attribute Write_Back_Write_allocated, Shareable by Device, then my program is ok and we don't have an ECC error
Do you have an idea ?
I tried to initialisze MMU following by ECC or ECC following by MMU , but We have always the same issue
Br
francois
Hi Francois,
Stack pointer is internal register of the core. I think you mean that your stack is located in OCRAM.
What error you talk about 1-bit correctable/noncorrectable error or other error?
MMU setting sharable by device and Write back does not have sense. Please send me you MMU setting.
You are using ASM. I'm not sure if I can help you with asm code.
/Jiri
hi jiri
I will create a project , for reproducing the issue and I will send you
Francois
hi
In this topic , I put a mini project for reproducing the issue about ECC on OCRAM
in file benchinit.c , we initialize the MMU and ECC on OCRAM
MMUConfigAndEnable();
ca5_ocram_ecc_stack_init(); -> in this assembler function , I enable the OCRAM ECC on SYSRAM1 , initialize the RAM , copy the stack
I set the MMU on OCRAM with the following parameters
REGION regionOcmc =
{
MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC, MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_NON_CACHEABLE, MMU_NON_CACHEABLE), MMU_REGION_NON_SECURE,MMU_AP_PRV_RW_USR_RW,
(unsigned int*)pageTable
};
With this setting when I call the function perfinit thta ccall pmuinit function , then we have an ECC error
perfinit
pmuinit
push {r0} -> write at @3f048FEA4 -> data 3F048FF0
...
pop {r0} -> ECC error at @ 3f048FEA4 , OCMFDR = 0x3F048FF0 0xFFFFFFFF ,OCMFTR=0x0082022F ( EFSYN=0x82,EFMST=0x2,EFW=0, EFSIZ=32 bits , EFPRT =Cacheable, Bufferable,Supervisor mode , data )
When I use the following MMU setting for OCRAM
REGION regionOcmc = { MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC, MMU_MEMTYPE_DEVICE_NON_SHAREABLE, MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
(unsigned int*)pageTable
};
then we don't have any ECC error
Do you have a sequence for initializing ECC on OCRAM when MMU is enable ?
Br
francois
Hi Francois,
It would require more time. I will focus on it next week (ww9).
/Jiri