working with the s12g128 processor:
the SWI reset command sends mirco to address 0x0 rather than the address programmed in the reset vectors @ 0xFFFA, 0xFFFC or 0xFFFE
I am not sure I understand the behavior you described.
The SWI is not reset oriented.
(Vector base + 0x00F8) Unimplemented opcode trap
(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request
The software interrupt (SWI) instruction initiates synchronous exception processing. First, the return PC value is stacked. After CPU context is stacked, execution continues at the address pointed to by the SWI vector.
I have attached an example I have tested the functionality. It worked without any problems. G128-CPU-SWItest-CW51.zip
Based on the some of the AN's and TP's I read I got the wrong impression that SWI was a software reset request.
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