I wanted to know i2c clock frequency is set to 400Khz or not for i2c0 bus & i2c1 bus?..
I found that in linux/arch/arm/mach-imx28/regs-i2c.h, it is set as below
#define BP_I2C_TIMING0_HIGH_COUNT 16
and compared with description from sect.27.5.2 "I2C Timing Register 0
(HW_I2C_TIMING0)" i.MX28 Reference Manual (rev.1, 9/2010):
"HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at
7 for 400KHz at 24mhz"
"But " BP_I2C_TIMING0_HIGH_COUNT " is not used in the I2c bus driver or I2c chip driver as it is only defined in the regs-i2c.h & more over the entire regs-i2c.h is being protected under the flag "#ifndef __ARCH_ARM___I2C_H" , could any body pls let me know how this is getting invoked in my I2c bus driver or i2c chip driver in the following file also,
Could you please let me know the i2c scl frequency is it configured for 400khz I2c0 bus & I2c1 bus & how this is getting invoked in the i2c driver code
Please kindly do the needful,
Thanks in advance